The ceramic capacitor cracked at the solder fillet.
Not during thermal cycling. Not during vibration. During field deployment, on a product that had passed 1,000 temperature cycles at -40°C to +85°C, with a ramp rate of 10°C per minute, with 20-minute dwells. The qualification binder was thorough. The test results were clean.
The failure mode was thermal shock. And thermal cycling — regardless of how many cycles, how extreme the temperature range, or how well the chamber was calibrated — cannot find it.
This is the distinction most test programs get wrong.
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The physics that separate thermal shock from temperature cycling
Temperature cycling and thermal shock both move a product between hot and cold. That surface similarity is what makes the confusion so persistent and so costly.
The difference is not the temperature range. It is not the number of cycles. It is the rate of change — and more precisely, what that rate of change does to a structure made of materials with different coefficients of thermal expansion.
In temperature cycling, the ramp is slow enough — typically 3 to 20°C per minute — that the product approaches thermal equilibrium continuously throughout the transition. The outer case, the PCB, the components, and the solder joints all move toward the same temperature at roughly the same time. The stress they experience is the accumulated fatigue of repeated differential expansion: real, damaging, and the target of temperature cycling as a test. But every point in the structure has time to respond to the thermal field around it.
In thermal shock, the transition happens in under 30 seconds — often under 10. The product moves from one extreme to the other before any internal thermal equilibrium is possible. The surface of a ceramic capacitor hits -55°C while the copper pad it's soldered to is still at +125°C. The body of a PCB is at +80°C while the components mounted on its top surface are already at -20°C. Those simultaneous temperature gradients — spatial, not temporal — create mechanical stresses that slow cycling never generates.
The failure mode thermal shock targets is brittle fracture under thermal gradient stress: the crack that opens across a ceramic capacitor body, the delamination that propagates through a laminate interface, the barrel crack in a plated through-hole that initiates not from fatigue but from the tensile stress of a thermal gradient that exceeds the material's fracture toughness in a single transition.
A material that is ductile and fatigue-resistant — copper, for instance — handles thermal shock well. A material that is brittle — ceramic, glass, certain polymers below their glass transition temperature — does not. The failure mode is fracture, not fatigue. And fracture, unlike fatigue, does not require cycles to accumulate. It requires sufficient stress applied in sufficient time. Thermal shock provides that. Temperature cycling does not.
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Two chamber designs for two different physics
Understanding the failure mode clarifies why thermal shock chambers are built differently from temperature cycling chambers — and why substituting one for the other produces results that are not comparable.
Two-zone (elevator) thermal shock chambers have a hot zone and a cold zone, typically stacked vertically. The product sits in a basket or fixture mounted on an elevator mechanism. When the transition command is issued, the elevator moves the product from one zone to the other physically — the product travels through a brief intermediate space and arrives in the opposite extreme within 10 seconds or less.
The two zones are independently conditioned and held at their setpoints continuously. There is no ramp. The product experiences a near-instantaneous step change in air temperature from the moment it enters the new zone. The thermal gradient across the product in those first seconds after transfer is the stress the test is applying.
Two-zone chambers are the reference design for thermal shock testing to IEC 60068-2-14 Test Method Na, which covers thermal shock with liquid or gas transfer between zones. The test note in IEC 60068-2-14 is explicit: the transfer time between temperature extremes must be specified and recorded, and it is typically required to be under 30 seconds. Shorter is more severe.
Single-zone thermal shock chambers achieve rapid transitions in a single workspace by using an exceptionally high-powered refrigeration and heating system — capable of driving temperature changes at 40 to 60°C per minute or faster. The product doesn't move. The chamber environment changes around it.
The single-zone approach is simpler mechanically — no elevator, no transfer mechanism, no fixture design constraints imposed by a basket — and allows continuous electrical monitoring of a powered DUT throughout the transition without the interruption of physical transfer. The tradeoff is that single-zone transition times are slower than a well-designed two-zone system. A chamber that achieves 30°C per minute in the single-zone configuration takes roughly six minutes to transition between -55°C and +125°C. A two-zone elevator system covers the same range in under 10 seconds.
For most commercial electronics test programs, single-zone rapid thermal cycling is sufficient. For aerospace qualification programs under MIL-STD-883 Method 1011 or high-reliability semiconductor testing, the two-zone system and its shorter transfer times remain the specification.
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The IEC standard that governs both — and how to read it correctly
IEC 60068-2-14, published by the International Electrotechnical Commission, covers both thermal shock and temperature cycling under the same standard number. This is the source of most specification confusion.
Test Method Na is thermal shock — rapid transfer between two zones at pre-conditioned extreme temperatures. It applies when the test specification requires the thermal gradient stress mechanism.
Test Method Nb is temperature cycling — controlled ramp in a single-zone chamber. It applies when the test specification requires accumulated fatigue from repeated differential expansion.
Both methods appear in IEC 60068-2-14. They test different things. When a customer specification says "test to IEC 60068-2-14," the critical question is which test method is referenced — Na or Nb. An engineer who runs Nb when Na was intended, or Na when Nb was intended, has run the wrong test. The product will pass or fail for reasons unrelated to the failure mode the specification was designed to evaluate.
In the automotive sector, ISO 16750-4 references IEC 60068-2-14 Test Nb for temperature cycling and defines the severity levels separately from thermal shock requirements. AEC-Q100, the automotive semiconductor qualification standard, specifies JESD22-A104 for temperature cycling and JESD22-A106 for thermal shock — separate standards for separate mechanisms. The automotive industry got this right at the specification level. Not every industry did.
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What thermal shock testing actually finds: five failure modes
The failure modes that thermal shock is specifically designed to precipitate — and that temperature cycling at any ramp rate will not reliably find:
Ceramic capacitor body cracking. Multilayer ceramic capacitors (MLCCs) are the most thermally shock-sensitive component in modern electronics. Their ceramic dielectric has a CTE of approximately 7–10 ppm/°C. The copper pad they're soldered to expands at 17 ppm/°C. The PCB laminate beneath that pad expands at 14–18 ppm/°C in-plane. During a rapid thermal transition, those CTE mismatches generate tensile stress in the capacitor body that can fracture the ceramic — not at the solder joint, but through the capacitor itself. The crack is typically invisible without microscopic inspection, creates no immediate failure, and manifests as a leakage current increase or dielectric breakdown weeks later in the field. Temperature cycling fatigues the solder joint at the termination. Thermal shock cracks the body. These are different components of the same assembly failing by different mechanisms.
Plated through-hole barrel cracking from gradient stress. As covered in the temperature cycling post, PTH barrel cracking can occur from fatigue accumulation under slow cycling. Thermal shock adds a second initiation mechanism: the instantaneous gradient across a thick laminate during rapid transition generates tensile stress in the z-axis that can crack a barrel without any fatigue accumulation. A single severe thermal shock cycle can initiate a crack that 500 temperature cycles would not.
Solder fillet cracking at brittle intermetallics. Lead-free solder alloys — primarily SAC305 (96.5% tin, 3% silver, 0.5% copper) — form intermetallic compounds at the interface with copper pads during reflow. Those intermetallic layers are brittle relative to the bulk solder. Under the instantaneous gradient stress of thermal shock, the fracture can propagate through the intermetallic layer rather than through the ductile bulk solder. The resulting failure surface looks different from fatigue cracking under slow cycling — it is flat, crystalline, and occurs with very few cycles.
Glass-to-metal seal integrity. Hermetic packages — used in aerospace, defense, and high-reliability electronics — use glass-to-metal seals to create airtight enclosures. Those seals are designed for steady-state CTE compatibility. Under rapid thermal transitions, the differential expansion between glass and metal generates stresses that the seal was not designed to withstand transiently. Thermal shock testing is the standard method for qualifying hermetic seal integrity in MIL-STD-883 Method 1014.
Conformal coating adhesion under gradient stress. A conformal coating applied over a PCB protects against moisture and contamination — but only if it adheres. Under thermal shock, the gradient between the coating and the substrate generates instantaneous peel stress at the interface. A coating with marginal adhesion that survives 500 thermal cycles can delaminate on the first severe thermal shock cycle, leaving the substrate it was protecting entirely exposed.
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The test parameters that define severity — and how to read them in a specification
Every thermal shock test is defined by four parameters. Changing any one of them changes the test severity in ways that affect which failure modes are precipitated and at what rate.
Temperature extremes (T-high and T-low). The wider the range, the larger the thermal gradient during transfer, the higher the stress. -55°C to +125°C is the standard high-reliability range for aerospace and military electronics. -40°C to +85°C is typical for commercial electronics. -40°C to +125°C is standard for automotive electronics under AEC-Q100 Grade 1. The range is not chosen arbitrarily — it should reflect the actual thermal environment the product will experience, multiplied by a severity factor appropriate for the reliability target.
Transfer time. The time between leaving one zone and stabilising in the other. This is the parameter most often under-specified. "Under 30 seconds" is the common shorthand. "Under 10 seconds" is the requirement for high-reliability aerospace applications. The shorter the transfer time, the steeper the thermal gradient imposed on the product, the more severe the test. A chamber that takes 45 seconds to transfer and one that takes 8 seconds are running meaningfully different tests at the same temperature extremes.
Dwell time. How long the product remains at each extreme before transfer. Dwell must be sufficient for the product to reach thermal equilibrium at the extreme temperature — not just for the chamber air to reach setpoint, but for the product itself to soak through. For a large assembly with significant thermal mass, 10 minutes is often insufficient. The consequence of insufficient dwell is that the product never reaches T-high or T-low before transfer, which reduces the effective temperature range and makes the test less severe than specified.
Number of cycles. Unlike temperature cycling, where cycles accumulate fatigue over many hundreds of repetitions, thermal shock often finds failures in the first 10 to 100 cycles — because the failure mechanisms are fracture-dominated rather than fatigue-dominated. JESD22-A106, the JEDEC thermal shock standard for semiconductors, specifies 1,000 cycles for high-reliability qualification. Most commercial programs specify 100 to 500 cycles. The right number depends on what failure mode you're looking for and how quickly it precipitates under the applied stress.
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The combination that no single test covers
Thermal shock and temperature cycling are not alternatives. They are complements.
Temperature cycling finds fatigue failures — the solder joint that cracks after 500 slow cycles, the barrel that fails after 1,000 thermal excursions. Thermal shock finds fracture failures — the ceramic capacitor that cracks on cycle 12, the hermetic seal that fails on the first liquid nitrogen transition.
A complete environmental test program for electronics includes both. The sequence typically runs thermal cycling first — to precipitate fatigue failures in the bulk of the qualification population — and thermal shock second, to specifically stress the brittle materials and interfaces that fatigue testing leaves unexamined.
Programs that run only one of these tests are making an implicit assumption: that the failure modes targeted by the other test are not relevant to their product. That assumption is sometimes correct. When it is wrong, the field return data eventually makes the point.
ESPEC North America's reliability engineering resources and Thermotron's application library both publish guidance on combining thermal shock and temperature cycling in reliability test programs — specifically on how to sequence them and how to interpret results that appear in one test but not the other.
For the full context of how thermal shock sits alongside humidity, vibration, and HALT in a complete test programme, the types of environmental test chambers post covers the hardware that each test method requires, and the HALT testing post explains how HALT's rapid thermal transitions relate to — and differ from — a standard thermal shock test.
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The question the qualification report doesn't answer
Most qualification test reports record the number of cycles, the temperature range, the pass/fail result, and not much else.
They don't record whether dwell time was sufficient for the product — or just for the chamber air. They don't record the transfer time between zones, or whether it was measured at the product surface or at the chamber sensor. They don't record the location of failures in the units that failed, or the failure mechanism in each case.
Without that information, a passed thermal shock test tells you the product survived a defined number of transitions at defined extremes. It does not tell you how close it came to failing, whether the test conditions were actually as severe as specified, or whether the failure modes the test was designed to find would have appeared with ten more cycles.
The thermal shock test report that is actually useful records all of those things — along with cross-sections of solder joints and ceramic components from units that survived to the end of the test, inspected for crack initiation that didn't propagate to failure during the test but would have in the field.
That last step — destructive physical analysis of survivors — is the one most programs skip. It is also the one that most often reveals that the qualification was closer than the pass result suggested.
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Next in this series: 50 Environmental Test Chamber Terms — Defined Without the Jargon · Temperature Cycling Testing: You're Probably Testing the Wrong Failure Mode · HALT Testing: The Test Designed to Break Your Product
Related: IEC, MIL-STD, ASTM, ISO: The Environmental Testing Standards Map Every Engineer Needs · Not All Environmental Test Chambers Are Equal · The Top 10 Environmental Test Chamber Manufacturers
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